In this edition of Embedded Edge with Nitin, there’s a bit of a RISC-V theme: I talk to SemiDynamics, a configurable 64-bit RISC-V startup coming out of stealth; then to Agile Analog, who’ve launched three new analog subsystems which package analog IP in digital wrappers, including RISC-V; and VyperCore, a processor startup that also launched with £4 million (about $5 million) seed funding and talked about its memory allocation management technology which will be deployed initially via RISC-V, but eventually to other architectures.
In the first interview, Roger Espasa, CEO and founder of Barcelona, Spain-based startup SemiDynamics, said the company launched the first fully customizable, 64-bit RISC-V core family for handling large amounts of data for machine learning, artificial intelligence and high-performance computing. I asked Roger to reveal more and understand how this is different to previous processors claiming to be fully customizable.
In the second interview, Chris Morrison, director of product marketing at Agile Analog, explains more about the company’s new digital wrapped analog subsystems, which claim to reduce the effort required to integrate multiple analog IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow and connected via a standard peripheral bus, such as AMBA APB.
And in my final interview, you’ll hear from Russell Haggar and Ed Nutting, co-founders of VyperCore, a new U.K. processor startup that received a record £4 million (about $5 million) in seed funding this month. They explain their innovation in memory allocation management that accelerates high-performance general-purpose compute workloads by a factor of up to 10×, without modifying the original code. I also asked why investors were so confident in the potential for their technology.
